1. Field of the Invention
The present invention relates to semiconductor substrates, and, more particularly, to a semiconductor substrate having through silicon vias and a method of fabricating the same.
2. Description of Related Art
Currently, packaging substrates are required to be configured corresponding to fine pitches of semiconductor chips so as to be integrated with the semiconductor chips. On the other hand, the coefficient of thermal expansion (CTE) mismatch between a chip, which generally has a CTE of 3 ppm/° C., and a packaging substrate, which generally has a CTE of 18 ppm/° C., easily causes large thermal stresses and warpages to occur, thus reducing the product reliability and resulting in the failure of a reliability test.
Accordingly, through silicon via interposer technologies have been developed to meet the miniaturization and high performance requirements of semiconductor packages. Referring to FIG. 1A, an interposer 1 is disposed between a packaging substrate 6 and a semiconductor chip 5 to alleviate the problem of CTE mismatch between the packaging substrate 6 and the semiconductor chip 5.
Generally, a plurality of through holes are formed in a silicon substrate 10 and filled with a conductive material so as to form a plurality of through silicon vias (TSVs) 11, and a redistribution layer (RDL) structure 12 is further formed on an upper surface 10a of the silicon substrate 10, thereby forming the interposer 1. The interposer 1 is further disposed on the packaging substrate 6 through a plurality of conductive bumps 60, and the semiconductor chip 5 is electrically connected to the RDL structure 12 of the interposer 1 through a plurality of solder bumps 50. Furthermore, an underfill 51 is filled between the interposer 1 and the semiconductor chip 5 to encapsulate the solder bumps 50.
However, the lower surface 10b of the interposer 1 is made of a dielectric material. Referring to FIG. 1B, when the interposer 1 is thin, the CTE mismatch will occur between the interposer 1 and the packaging substrate 6. As such, thermal stresses and warpages can easily occur to the interposer 1, thereby reducing the product reliability and resulting in failure of a reliability test.